(C) Yann Guidon 2001 (
whygee@f-cpu.org
)
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Scheduling of one instruction (2)
Hazard detection with a scoreboard
Every register is associated to a "not ready bit"
The bit is set when the instruction is issued
The bit is reset when the scheduler commands a write to the register.
The decode pipeline is stalled if all the necessary bits for the current instruction are not cleared.
This scheme is scalable almost in O(n) with the number of concurrently decoded/executed instructions