(C) Yann Guidon 2001 (
whygee@f-cpu.org
)
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Variable latency
Every Execution Unit of the F-CPU
is dedicated to a particular type of operation :
ROP2 : bit-to-bit boolean operations :
1 cycle
SHL : SIMD bit/byte shuffling,
1 or 2 cycles (?)
INC : SIMD
1 (inc/dec/neg/abs/lsb...) or 2 (cmp/min/max...) cycles
ASU : SIMD integer addition and substraction with carry and saturation :
2 cycles (general case), 1-cycle for 8-bit add/sub
IMU : SIMD Integer Multiply Unit (+ MAC) :
6 cycles / 64-bit (MR design)
IDU : SIMD Integer Divide Unit :
1 cycle per bit
LSU : (not SIMD...)
2 cycles (LSU hit)
POPC/ECC, LNS ASU ... :
(?)
EUs are "LEGO bricks" with a particular and deterministic latency. They are all SIMD-capable and are duplicated when the register width increases. The SIMD size and "chunck" size are implementation-dependent.