(C) Yann Guidon 2001 (whygee@f-cpu.org) slide 8 / 18
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Scheduling of one instruction

        Fetcher : 1 cycle (transparent) {bypass possible when cache miss}
decoder/R7 read : 1 cycles (more if stall)
Issue/Xbar read : 1 cycle (unless bypass possible)
             EU : 1+ cycle (latency depends on the unit, see slide #5)
           Xbar : 1 cycle (here we don't care about the scheduling...)
 Register write : 1 cycle