f-cpu/vhdl/eu_rop2/README.txt
created Thu Aug 23 01:10:22 2001 by whygee@f-cpu.org

this is a newer version of the ROP2 unit.
it is more up to date than the version released 1 year ago
and it comprises the COMBINE and MUX operation modes.

The unit is now split into 2 files, each acting at a separate
level in the pipeline. The usual part is done as always, after
the Xbar level. It performs the operations.
The other part is a pure control signal stuff : the operation
function is decoded (3->4 bits) and amplified (the fanout
would be four time 1 to 64 bits in the ROP2 unit itelf).
Now the four function signals amplified 16x and the last
stage (4x fanout) is done after the stage flip-flops.
i guess that 4x is a reasonable fanout, at least much more
acceptable than the previous version :-)

The flip flops are implemented outside of the design,
in the top level file (not available yet).
