f-cpu/c/jaap.txt
notes about fcpusim by: Jaap Stolk (JWS) jwstolk@yahoo.com
version: Tue Jul 16 10:25:57 CEST 2002

-notes are in no particular order.
-feel free to comment

 HELP !! some things that i need a bit of help on:

 - how do i read a key from stdin in linux ?
   (I can only do it if i press <enter> after each key)

 - variable naming a bit of a mess, the naming in the VHDL code duos 
   not look very consistent.. (i.e. mixed unit_out and unit_y ).

 some ramblings about a simulator:

I seem to have confused the D-latches wetween the pipeline stages
with flip-flops, sorry, i'll try and correct it later.

how it works:
the simulator simulates each unit of the f-cpu. every unit has input and
output values. the simulator runs all units (in a random order) and then
connects all units by copying output values to input values. this
copying-stage simulates the Filp-Flops in the f-cpu. if a unit takes more
than one stage, it has internal Filp-Flops/values as well.

detecting / counting / visualising pipeline stalls would be handy for
optimising code. (it also needs to show the reason that caused the stall)
this information could even be used for automatic optimisation ( in a
compiler ??)

compile the simulator:
 - add these files to a (installed) YG snapshot (in the /f-cpu/c/ directory )
   (the simulator itself duos not need to be installed)
 - run runme.sh in the /c/toplevel directory.

interface:
I would like a (text based) interface that shows the most important CPU
status (including a used/free pipeline view), and could show each unit
status as well. (i will try to move the show_unit_xxx function to the units
directory)

the used/free pipeline view is the same as the score board view !?

f = f-cpu
i = inc
2 = rop2
a = asu
s = shl
p = popc
b = bist
v = div
m = mul
  = sr's (i really want to use "s" for shuffle and "r" for registers)
x = xbar
r = registers ( R/W ports)
o = scoreboard
d = data unit/mem
c = code unit/mem
t = tlb's (data and code?)

speed:
i might optimise the code a bit more, but the only reason will be to be able to
test run programs in less than an hour.
this simulator is not intended to be fast, its written to test/try different
configurations of the f-cpu, and find bottlenecks, optimal TLB size, etc.
it will be possible to add/remove optional EU's, an it should be possible to
run it with 128 / 256 bit registers.
olso testing different configurations of the X-bar would be interesting.
(shearing Xbar ports between different EU's) or even experiment with the
number of read/write busses of the Xbar ?

every simulated unit must be cross tested with the corresponding VHDL unit

it should be possible to run the simulator at maximum speed by not selecting
any particular status view. also run until next call/ret would be nice.
(or even put breakpoints on the use of register / memory / units / etc)

the copying stage that simulates the ff might be removed, if the units are
run in the correct order, but at some point (xbar?) they are still needed
to close the loop.

the actual f-cpu has no ff for the register unit, i change the simulation to
work the same way.

it would be nice to mix C and VHDL units, this could be done if the VHDL units
read/write there input/output ff from/to files that are read by the simulator.

a "save_state" function might be nice, if its saved in a compact but readable
text format, it could be e-mailed, and someone else could look at that
situation? ( -> copy past the terminal text would do the same job ?)

what programs i would like to run on this simulator:
- things like the Winograd DCT algorithm, and other critical routines
  i.e. things that today's (and tomorrows) programs spend most cycles on
- L4 (or other micro kernels)
- programs to test different IRQ I/O designs

i could add a history buffer (ff status for the last 100 cycles), so we
could trace backward and find the cause of a pipeline stall its.
(when walking back, the ff states are only changed, the units are not run)

the simulator needs to show the ASM (and C?) code that is executed, as well as
(parts of) memory.

would it be possible to add a <script> </script> tag to the c files and turn
it into an on-line simulator ?? (i.e. type a few binary instructions and see
them flow threw the f-cpu ?).

at some point the simulator needs to be connected to (simulated?) I/O
to start with: a serial port (for console).

simulator also needs to test the power up (random start) sequence!.
this should be done by the BIST unit.

also show a TLB's status screen.

