TODO for YG

done but not considered as satisfying and completed :
- better test for Register set + support for
   multiple sets inside the bank (i just tightened
   the tests --> the rest will be done in BIST)
- integrate Riviera  --> done

in the queue :
- finish popcount --> modify rand() too
- finish INC --> redesign Etienne's files + rand
- make BIST ( MISR + vector generator + controller + tests )
- Then : Xbar, scheduler...

Additions on Sat Jul  6 08:11:52 CEST 2002 :

- make C descriptions of each unit
   <---- make a F-CPU C library !!!!
- switch to procedural stuffs
- remove instances when unneeded,
- make '87-style instanciations
- update to MR CIAdd with carry
- update MR's READMEs and the VHDL-HOWTO

Sun Jul  7 07:03:03 CEST 2002
- error on sram3r2w with Riviera (???)
- redesign ROP2  --> done
- design a C vs VHDL verification framework  --> done

Mon Jul  8 01:33:00 CEST 2002
- Etienne maintains his INC unit and will
  redesign it, Cedric must change the manual
  concerning ROP2 and INC
- cleanup the files

Thu Jul 11 07:18:04 CEST 2002
- problems with riviera and the register set !
  synchronicity and sensitivity lists...
  basicly, it must be rewritten.
  particularly, the write latency is not well done.

Sun Jul 21 06:57:47 CEST 2002
- polish all the sources
- create the cross-langage test libraries

Fri Jul 26 19:21:39 CEST 2002
- rewrite and adapt all the units in C and VHDL
  so it uses the same tests
- include timing (cycles + states)  ---> done for ROP2
    --> removed (collision with Xbar + unwanted states)

Sat Jul 27 08:01:04 CEST 2002
- take Jaap's changes (concerning stalls) into account.
    --> done : ROP2 is not concerned in the end.

Sun Jul 28 01:45:27 CEST 2002
- restore the full opcode map and the flags ---> ASM !!!
- reorganise the opcode map

Mon Jul 29 00:56:11 CEST 2002
- find another bit ==> implement new kind of MSB flag
- ROP2 is finished (C&VHDL) but registers are not ok in VHDL.
