f-cpu/c/registers/README.txt
created Sat Jul 20 20:44:55 CEST 2002 by whygee@f-cpu.org

The register set is a particular part of the pipeline.
it has a read and write latency of one cycle.
The bypasses are done at the Xbar level. It is not clear
yet how the latencies will be simulated in C.

Warnings :
 - i have not yet checked where the condition is (R0 or R2 ?)
 - the MSB flag is hooked to the 63th bit of the register.
   there will probably be a problem when 128+ versions will appear.
 - the reg_FP flag is hooked to zero. any use should trigger a trap
   as long as FP is not implemented !!!
 - the alignment flags should be ok, but check them anyway.

 - i have modified most files today so it seems to work
 - the test does not cover much.
