f-cpu/INSTRUCTIONS.txt
created Sun Aug  5 18:48:13 2001 by whygee@f-cpu.org
updated Sun Aug 19 04:54:30 2001
updated dim mar 31 00:02:21 2002 : well in fact, a lot of things
are broken so don't rely on this yet.

Supported instructions in this implementation are :

NOP
(C)MOVE
LOADCONS(X)
ROP2/MUX
ROP2I

This is well enough to test the first parts of the scheduler.

Changes made to the manual :

* MOVE takes 1 more cycle :
   decode - Xbar read - Xbar write - Writeback
  but there is no incidence on the actual code performance.

* Instructions with 8-bit immediate data are not optional,
  but belong to the "core", since the overhead is not worth
  the worries.

* ROP2 instruction format has been heavily changed
  - MUX instruction has been added, as well as AND and OR "combine"
  - the function fields, the mode field and most of the flags have
    been moved.

* The bit ordering in the instructions is completely reversed.


PROPOSALS FOR NEW OPCODES :
* Sign extension, probably in SHL. This frees a bit in the MOVE
   instruction. Behaviour and details are currently not yet discussed.
==> MR has proposed "widen(s)" for that instruction.
* Scatter/Gather : reserving some opcodes will be enough. Not used in FC0.
* NOP-N : used when aligning instruction to cache line boundaries.
* Bitfield insertion/extraction in SHL. undertermined strategy yet.
  MUX helps however.
* LOADADDR is not enough, we have to add a kind of "LEA", a specific
ADD instruction for pointers only : without SIMD but TLB check.
same form as add/sub, but without the usual options.
* conditional LOAD and STORES ==> 4th condition is "dirty pointer"
* one instruction that performs a logic=>physical address translation
  (and/or vice versa)
* the BIST unit provides new opcodes : reading/writing the MISR and
  creating specific vectors/data.
