F-CPU project, nov. 29 2000 by Yann GUIDON (whygee@f-cpu.org)

This file describes the capabilities of the current version of
this package. Please update this file if you modify something.

             +------------+
             | MAX. CHUNK |
------+------+-----+------+---------+----------------
UNIT  | SIMD | 64b | 128+ | latency | architectures 
------+------+-----+------+---------+----------------
INC   |      |     |      |    1    |
ASU   |   *  |  *  |      | 1 or 2  | EU_ASU:Struct_1 in f-cpu/vhdl/eu_asu/asu.vhdl
IMU   |   *  |  *  |  ?   | 3,4,5,6 | EU_IMU:Struct_1 in f-cpu/vhdl/eu_imu/imu.vhdl
LSU   |      |     |      |  (2?)   |
IDU   |      |     |      |variable |
SHL   |   *  |  *  |      | 1 (2?)  | EU_SHL:Struct_1 in f-cpu/vhdl/eu_shl/shl.vhdl
ROP2  |   *  |  *  |  *   |    1    | EU_ROP2:arch1   in f-cpu/vhdl/eu_rop2/rop2_unit.vhdl
POPC  |   *  |  *  |      |    4    | EU_POPC:Struct_1 in f-cpu/vhdl/eu_popc/popc.vhdl

The maximum chunk size refers to the larges integer numbers
that can be managed : this is independent from the register
size. ROP2 can scale up rather well and be as large as wanted.
Some other units are still undefined, it sometimes
doesn't make sense to have larger versions. Anyway, the 128+
versions will still provide downsized versions of the
operations.

Most units can be duplicated to form a SIMD unit
as large as the register, except LSU for example.


Mon Sep 10 00:01:53 2001
32-bit support is dropped : not encouraged or supported.
Use LEON instead, or use 32-bit only code attributes.


Sat Jun 29 08:51:00 CEST 2002
SHL is released but only provides 64-bit chunks :
it is not possible to shift 128 bit registers,
except in SIMD mode where each chunk is independent.
That's a worrisome part of the F-CPU ISA. A new
definition and version should appear in the future.


Sat Jul 27 23:09:40 CEST 2002
latency of MR's multiply unit :

  size     Low    High
 8 bits     3       4
16 bits     4       5
32 bits     5       5
64 bits     6       6
