        F-CPU Design requirements

Without regard to any dissenting oppinions, I declare theze to be the design
requirements of the F-CPU.

        1. Compatability with the latest Ev6 bus specifcation

        2. A memory throughput of 1.5 Gigabytes per second

        3. A "Load-Add-Store" throughput of 750 megabytes/second. where one
operand must be loaded, added to a constant, and written to memory.

        3. A maximum memory read latancy of 10 nanoseconds

        4. nominal interrupt response time of 200 nanoseconds

        5. No stupid limitations.

[opt]   6. Some crazy funky architecture that deserves to be called "GNU". =)
No risc, No Cisc... GNU!!! =)  All computer languages have a
"Universal Machine" I propose that part of the task state be a
representation of that "Universal Machine" that is loaded into the processor
each time the process is loaded. Interrupts will neccessarily run on the
processor's VLIW substrate.

        7. Each unit of execution or instruction shal have a latancy not
greater than 20 nanoseconds.

Okay, additional metrics may be added as the project evolves. =)
