F00 Microcode Version 0.02
==========================
22-9-99  Jeff Davies

This is a stab at the microarchitecture microcode (as executed by the state machine)
for F00 CPU version 0.02 (see diagram).

Please note the addition of the string "/temp" to the name of the data address latch.
I decided to use this register for MOV and SUPERSWAP.


*NOTE NOT DISPLAYED ON DIAGRAM, FOR EVERY Tristate buffer, there is a signal "Enable"
which converts the output from high impedance to low impedance (either to +Vcc or
0V according to the input logic). i.e a standard tristate buffer.
Most Tristate buffers are 32 bit wide with the exception of user status reg's Buffer #1
which is only 1 bit wide (allows the Zero bit to be written to).

Instruction Fetch Sequence 
(number is clock cycle, all events within a cycle occur in parallel)
====================================================================
1. ProgramCounter.Count(H)
2. ProgramCounter.Count(L)
   Buffer6.Enable(H)
   Buffer8.Enable(L)
   ExternalMemory.Read(H)
   ExternalMemory.Code(H)
   ExternalMemory.Memreq(H)
   Buffer17.Enable(H)
   InstructionLatch.Load(L)
3  InstructionLatch.Load(H)


MOV
===
1.  RegisterFile.CS(H)
    RegisterFile.OE(H)
    DataAddressLatchTemp.Load(L)
2.  DataAddressLatchTemp.Load(H)   
3.  InstructionExecutionStateMachine.2ndOperandBuffer.Enable(H)
{note the above is not shown, but gates the 5 bits in the instruction word
through to the address of the RegFile}
    RegisterFile.OE(L)
    RegisterFile.CS(L)
4.  Buffer14.Enable(H)
    RegisterFile.WR(H)
    RegisterFile.CS(H)


I hope to flesh out these in the coming weeks, and then produce a design for the
IESM (Instruction Execution State Machine) unit.


To Do:
======
AND		
OR		
NOT		
SHIFTL/R[C]
ROTATER/L[C]
ADD
LOAD/STORE
	//MOVE is above//
SUPERSWAP
LOADIMMEDIATE
JUMPABS
JUMPRIMM[C]
JUMPREL
SYSCALL

