Previous Next Table of Contents

11. Virtual memory: pure paging

The F-CPU architecture does not implement segmentation: pure paging is used, with 8KB pages. The MMU is particularly simple: a 64-entry TLB is used like in MIPS.

In parallel with the fixed size 8KB paging scheme, the F-CPU architecture makes use of an implementation dependent number (minimum of two) of variable-sized pages, ranging (in powers of 2) from 16KB up to the entire address space. These variable-sized pages can be used , for example, to map an entire video frame buffer in a single step, or to assign a fixed mapping to the OS kernel.

Like in MIPS, a TLB miss will trigger an exception, which is handled by context switching to the kernel. With a 64-bit address space, it was judged that an inverted hash table implementation would be more effectively implemented in software rather than in hardware, and would yield adequate performance.


Previous Next Table of Contents