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8. Instruction Classes

We'll use the following broad instruction classes defined by H&P for the DLX architecture:

  1. Moves (H&P defines this as load/store instructions). Since we specified that our coprocessors would be designed using TTA logic, our FP and block move instructions are included in this instruction class.
  2. ALU operations.
  3. Branches and Jumps.
  4. We'll add a fourth class for special instructions e.g. HALT, so: Special.

In fact H&P had defined a separate instruction class for FP, but we managed to fold that into the Moves instruction class (we are really pushing RISC philosophy, here: simplify, simplify). ;-)

8.1 Move instructions

Move instructions support all data sizes up to and including 64 bits, as expected. Signed and unsigned byte, half-word and word are accounted for, as well as double. (128-bit moves?)

The F-CPU recognizes three distinct address spaces: I/O, coprocessor and memory.

8.2 ALU instructions

Logical and arithmetic operations operate on three registers or two registers and a 16-bit immediate operate.

8.3 Branches and Jumps

For lack of imagination, we adopted almost exactly the same control flow instructions as DLX:

8.4 Special


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