FCPU MANUAL REV. 0.1 |
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Everything in this document is furiously preliminary and changes often without notice. Please keep in touch with the group on the mailing list and check the latest updates on the official F-CPU web site.
This document is (C) The F-CPU Group Design Team and is a collaborative work. Anybody can participate to the F-CPU effort and become a team member by subscribing to the mailing list and taking part to the discussions. You are welcome to submit your ideas and report errors. We are conscious that this document still contains errors but we are working on (or around ?) them constantly.
The manual is split in several parts so any part can be updated independenly, thus easing the parallel work of the group members : a single modification can be made without needing to have the whole document in its latest updated form.
Why a HTML manual ? Because it is the most portable and readable publication format. One can find a Web browser on almost any machine of this planet, and it is also very compact, it has a certain "style" that is usually masked in other publication formats, anybody can modify the source with his text editor and immediatly enjoy the result without the need of a compilation of any kind. I agree that it lacks the possibility to say which page contains what, but this detail is left to the people who will translate this manual in other formats before printing.
created July 8, 1999 by Whygee (Yann Guidon)
July 10 : added some more.
11th: adapted for converstion to PDF
with HTMLDOC.
8/2, 8/8, 8/9, 8/13: added yet some more.
8/25 : reworked a bit (what-why, TTA, endianness, paging, jump station...)
11/5 : merged with some other non-architectural contents.
11/16 : revamped it all for HTML back.
You can contact the author of this document by e-mailing Yann Guidon at
whygee@mime.up8.edu.
The official F-CPU site : http://f-cpu.tux.org/
The latest update of the F-CPU Manual : http://www.mime.up8.edu/~whygee/fcpu_manual.zip
The mailing list : http://www.eGroups.com/list/f-cpu
Part 2: General description of the F-CPU
2.1 The main chacteristics
2.2 The instructions are 32-bit wide
2.3 Register 0 is "read-as-zero/unmodifiable"
2.4 The F-CPU has 64 registers
2.5 The F-CPU is a variable-size processor
2.6 The F-CPU is SIMD-oriented
2.7 The F-CPU has generalized registers
2.8 The F-CPU has special registers
2.9 The F-CPU has no stack pointer
2.10 The F-CPU has no condition code register
2.11 The F-CPU is endianless
2.12 The F-CPU uses paged memory
2.13 The F-CPU stores the state of a task in Context
Memory Blocks
2.14 The F-CPU can use the CMBs to single-step tasks
2.15 The F-CPU uses a simple protection mechanism
Part 3: General description of the FCPU Core #0
3.1 About the FC0 core
3.1.1 The FC0 is superpipelined
3.1.2 The FC0 core implements an out of order
completion pipeline
3.1.3 The FC0 uses a scoreboard
3.1.4 The FC0 uses a crossbar
3.2 Evolution of the FC0
3.3 The FC0 Execution Units
3.3.1 The "ROP2" unit
3.3.2 The "bit scrambling" unit
3.3.3 The "increment" unit
3.3.4 The add/sub unit
3.3.5 The integer multiply unit
3.3.6 The integer divide unit
3.3.7 The Load/Store unit
3.3.8 Other units
Part 4: Advanced topics
4.1 Foreword
4.2 The exceptions
4.3 The Smooth Register backup mechanism
Part 5: The F-CPU Instruction Set Architecture
5.1 Designing an instruction set
5.2 Instruction formats
5.3 The ISA modularity
5.4 The 2r1w format and its extensions
5.5 Flags
5.5.1 Size flags
5.5.2 SIMD flag
5.5.3 IEEE flag
5.5.4 saturate/carry flag
5.5.5 other flags / reserved fields
Part 6: F-CPU Instruction Set draft
currently in construction.
6.1 Data Manipulation
6.1.1 Core Arithmetic
6.1.1.1 add
6.1.1.2 sub
6.1.1.3 mul
6.1.1.4 div
6.1.2 Optional Arithmetic
6.1.2.1 addi
6.1.2.2 subi
6.1.2.3 muli
6.1.2.4 divi
6.1.2.5 mod
6.1.2.6 modi
6.1.2.7 mac
6.1.2.8 popcount
6.1.3 Optional increment-based
6.1.3.1 inc
6.1.3.2 dec
6.1.3.3 neg
6.1.3.4 bit scan
6.1.3.5 cmpl
6.1.3.6 cmple
6.1.3.7 cmpli
6.1.3.8 cmplei
6.1.3.9 abs
6.1.3.10 max
6.1.3.11 min
6.1.3.12 maxi
6.1.3.13 mini
6.1.3.14 sort
6.1.4 Core Shift and Rotate
6.1.4.1 shiftl
6.1.4.2 shiftr
6.1.4.3 shiftra
6.1.4.4 rotl
6.1.4.5 rotr
6.1.5 Optional Shift and Rotate
6.1.5.1 shiftli
6.1.5.2 shiftri
6.1.5.3 shiftrai
6.1.5.4 rotli
6.1.5.5 rotri
6.1.5.6 bitop
6.1.5.7 bitopi
6.1.6 Core Logic
6.1.6.1 logic
6.1.7 Optional Logic
6.1.7.1 logici
6.1.8 Optional SIMD Packing
6.1.8.1 mix
6.1.8.2 expand
6.1.8.3 sdup
6.1.9 Floating Point Operations
6.1.10 Optional Misc.
Figures :
figure 1 : The pipeline is folded around the Xbar.
figure 2 : The first F-CPU chip proposal.
figure 3 : A more precise, first-attempt F-CPU description.
figure 4 : A third F-CPU description
figure 5 : Detail of the ROP2 unit.
figure 6 : Overview of the Scrambling unit
figure 7 : Detail of one bit of the SRB flags
and decision mechanism.
figure 8 : Preliminary overview of the instruction forms
figure 9 : Description of the mix instruction>
figure 10 : Description of the expand instruction