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6. Early architectural choices

6.1 Hard choices

Early in the development of the F-CPU architecture, some hard technical choices were made. It is likely that the F-CPU architecture will have the following features:

  1. 64-bit internal data paths (i.e. this is a 64-bit architecture).
  2. Standard Von Neumann CPU<->memory architecture.
  3. 64-bit address space.
  4. Virtual memory support.
  5. Kernel and user operating modes.
  6. Co-processor support (FP, Graphics, etc...) on a separate (internal) bus.
  7. Designed for Y2K-current process technologies (0.25 micron or smaller).

6.2 Firm choices

Some other architectural choices are being dictated by the desire to innovate and improve upon current CPU architecture design practices. These choices are more questionable compared to the hard choices listed in the previous subsection, and yet once a consensus is reached over these choices, the F-CPU architecture will be in many ways determined. At we write these lines, these firm choices are:

  1. A memory-to-memory (m2m) / RISC mixed architecture (this is explained below).
  2. Both big-endian and little-endian modes supported (H&P pages 73 and C-12).
  3. Memory windows with 32 user-visible virtual registers. The number of memory windows is implementation dependent, with a minimum of 2 windows. These memory windows can be thought of as virtual register banks. They are used to accelerate context switching (they are not used to accelerate procedure calls, as are register windows in the SPARC architecture).
  4. Three operand instructions, as per standard RISC practice.
  5. A 32-bit fixed length instruction format, also as per standard RISC practice.
  6. Separate I/O, coprocessor and memory addressing spaces. The I/O and coprocessor addressing spaces (16 bits each) only allow Moves. The I/O addressing space is protected (only accessible in supervisor mode). The coprocessor addressing space is user-visible.
  7. N-stage pipelined operation, where n is implementation dependent.
  8. Hardware integer multiply and divide.
  9. FP coprocessor implemented as coprocessor mapped Transport Triggered Architecture (TTA) logic (the presence of an FPU is implementation dependent).
  10. Block Move coprocessor also implemented as coprocessor mapped TTA logic (the presence of a Block Move coprocessor is implementation dependent).
  11. No condition codes, a la MIPS.
  12. Immediate operands are limited to 16-bit size (due to the fixed 32-bit instruction length).
  13. CPU Control Registers (CCRs) are mapped in the first half (32KB range) of the coprocessor address space.

6.3 Soft choices

Many ideas are still floating around on the various Freedom Project mailing lists.


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