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We'll use the following broad instruction classes defined by H&P for
the DLX architecture:
- Moves (H&P defines this as load/store instructions). Since we specified
that our coprocessors would be designed using TTA logic, our FP and block move
instructions are included in this instruction class.
- ALU operations.
- Branches and Jumps.
- We'll add a fourth class for special instructions e.g. HALT, so: Special.
In fact H&P had defined a separate instruction class for FP, but we
managed to fold that into the Moves instruction class (we are really pushing
RISC philosophy, here: simplify, simplify). ;-)
Move instructions support all data sizes up to and including 64 bits, as
expected. Signed and unsigned byte, half-word and word are accounted for, as
well as double. (128-bit moves?)
The F-CPU recognizes three distinct address spaces: I/O, coprocessor and
memory.
Logical and arithmetic operations operate on three registers or two registers
and a 16-bit immediate operate.
- Logical: AND, OR, XOR, NAND, NOR, NXOR.
- Arithmetic: ADD, SUB, MULT, DIV; signed and unsigned. MULT and DIV store
their result in two consecutive virtual registers (unlike MIPS, but very much
like SPARC).
- Shifts and Rotates: rotates as well as logical and arithmetic shifts, left
and right, 1 to 64 bits.
- Set conditional.
For lack of imagination, we adopted almost exactly the same control flow
instructions as DLX:
- Branch on zero/not zero.
- Unconditional Jump.
- Jump and Link.
- SYS. System call exception (H&P use TRAP). Switches to MW0, entering
supervisor mode. Unlike DLX, this is not a vectored trap: the OS kernel is
assumed to have a single entry point.
- RFE. Return from exception. Switches back to the previously active MW,
restores user mode.
- HALT. Stops and powers down the CPU.
- STI. Enable maskable interrupts.
- CLI. Disable maskable interrupts.
- LCX. Locked compare and exchange. Compares and exchanges the contents of
a register with the contents of a memory address, pointed to by another register
plus 16-bit displacement.
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