Appendix B :
This document is a first census of the available instructions. It is currently used to determine the efficiency of the instruction word format as well as the structure of the needed decoding logic.
Core : | there is an asterisk if implementating this instruction is mandatory. |
F0 : | this instruction will be implemented in the F0 chips. |
Form : | what ressources/fields are used at decode time. |
SIMD : | if the instruction uses the SIMD flag in the opcode. |
EU : | Execution Unit that the instruction uses. |
1C : | one register is used as a condition and its value is not used as such. |
(P) : | one register is a pointer. |
(I) : | one register is used as a pointer to instructions. |
(t0) : | test if register operand is zero. |
(t0-> T) : | trap if register operand is zero. |
3r : | read three registers. |
2r : | read two registers. |
1r : | read one register. |
i8 : | 8-bit immediate. |
i16 : | 16-bit immediate. |
1w : | write one register. |
(tMSB) : | test is MSB (bit sign) is set. |
! : | SIMD has no meaning here (it is implicit or irrevelant). |
Preliminary opcode map overview :
# | major opcode | names and mnemonics | C o r e | F 0 | Form | S I M D | EU | remarks |
1 | OP_ADD | add, adds, addu | * | * | (t0) 2r1w | * | ASU | 1 bit left for LNS or fractional (Q) format |
2 | OP_ADD | addc | * | (t0) 2r2w | * | ASU | (idem, LNS/Q) |