SysAD Bus Pins
SysAD[0:63] |
in/out |
Processor Address/Data Bus. Operates as per MIPS R4x00 SysAD Bus. |
SysADC[0:7] |
in/out |
Processor Address/Data Check Bus. Operates as per MIPS R4x00 SysAD
Bus. |
SysCMD[0:8] |
in/out |
Processor Command Bus. Operates as per MIPS R4x00 SysAD Bus. |
RdRdy |
out |
Indicates that the corelogic is ready to acceot a new read transaction.
Operates as per MIPS R4x00 SysAD Bus. |
WrRdy |
out |
Indicates that the corelogic is ready to accept a new write transaction.
Operates as per MIPS R4x00 SysAD Bus. |
ExtRequest |
out |
Indicates that the corelogic needs to use the SysAD bus. Operates as
per MIPS R4x00 SysAD Bus. |
Release |
in |
Indicates that the processor has released the bus to the corelogic.
Operates as per MIPS R4x00 SysAD Bus. |
ValidIn |
in |
Indicates that data placed on the SysAD/SysCmd busses by the processor
is valid. Operates as per MIPS R4x00 SysAD Bus. |
ValidOut |
out |
Indicates that data placed on the SysAD/SysCmd busses by the corelogic
is valid. Operates as per MIPS R4x00 SysAD Bus. |
IvdAck |
out |
Indicates the successful completion of a pending processor invalidate
or update request. Operates as per MIPS R4x00 SysAD Bus. |
IvdErr |
out |
Indicates the unsuccessful completion of a pending processor invalidate
or update request. Operates as per MIPS R4x00 SysAD Bus. |
PCI Bus Pins
PciAD[0:31] |
in/out |
PCI Address/Data Bus. Operates as per PCI Specification 2.1 |
PciPar |
in/out |
PCI Parity Indicator. Operates as per PCI Specification 2.1 |
PciReq[0:7] |
in |
PCI Bus Request Signals. Operates as per PCI Specification 2.1 |
PciGnt[0:7] |
out |
PCI Bus Grant Signals. Operates as per PCI Specification 2.1 |
PciClk |
out |
PCI Clock Signal. Operates as per PCI Specification 2.1 |
PciC/BE[0:3] |
t/s |
PCI Command/Byte Enable Bus. Operates as per PCI Specification 2.1 |
PciReset# |
out |
PCI Reset Signal. Operates as per PCI Specification 2.1 |
PciFrame# |
s/t/s |
PCI Cycle Frame Signal. Operates as per PCI Specification 2.1 |
PciTRdy# |
s/t/s |
PCI Target Ready Signal. Operates as per PCI Specification 2.1 |
PciIRdy# |
s/t/s |
PCI Initiator Ready Signal. Operates as per PCI Specification 2.1 |
PciStop# |
s/t/s |
PCI Transaction Stop Signal. Operates as per PCI Specification 2.1 |
PciLock# |
s/t/s |
PCI Bus Lock Signal. Operates as per PCI Specification 2.1 |
PciIDSel[0:7] |
out |
PCI Initialization Device Select Signals. Operates as per PCI Specification
2.1 |
PciDevSel# |
s/t/s |
PCI Device Select Signal. Operates as per PCI Specification 2.1 |
PciPErr# |
in |
PCI Parity Error Signal. Operates as per PCI Specification 2.1 |
PciSErr# |
in |
PCI System Error Signal. Operates as per PCI Specification 2.1 |
PciSBO# |
in/out |
PCI Snoop Back Off Signal. Operates as per PCI Specification 2.1 |
PciSDONE |
in/out |
PCI Snoop Done Signal. Operates as per PCI Specification 2.1 |
INTA# - INTD# are connected to the Programmable
Interrupt Controller. |
AGP Bus Pins
AgpAD[0:31] |
in/out |
AGP Address/Data Bus. Operates as per AGP Specification 2.0 |
AgpPar |
in/out |
AGP Parity Indicator. Operates as per AGP Specification 2.0 |
AgpReq |
in |
AGP Bus Request Signal. Operates as per AGP Specification 2.0 |
AgpGnt |
out |
AGP Bus Grant Signal. Operates as per AGP Specification 2.0 |
AgpClk |
out |
AGP Clock Signal. Operates as per AGP Specification 2.0 |
AgpC/BE[0:3] |
t/s |
AGP Command/Byte Enable Bus. Operates as per AGP Specification 2.0 |
AgpReset# |
out |
AGP Reset Signal. Operates as per AGP Specification 2.0 |
AgpFrame# |
s/t/s |
AGP Cycle Frame Signal. Operates as per AGP Specification 2.0 |
AgpTRdy# |
s/t/s |
AGP Target Ready Signal. Operates as per AGP Specification 2.0 |
AgpIRdy# |
s/t/s |
AGP Initiator Ready Signal. Operates as per AGP Specification 2.0 |
AgpStop# |
s/t/s |
AGP Transaction Stop Signal. Operates as per AGP Specification 2.0 |
AgpLock# |
s/t/s |
AGP Bus Lock Signal. Operates as per AGP Specification 2.0 |
AgpIDSel |
out |
AGP Initialization Device Select Signal. Operates as per AGP Specification
2.0 |
AgpPErr# |
in |
AGP Parity Error Signal. Operates as per AGP Specification 2.0 |
AgpSErr# |
in |
AGP System Error Signal. Operates as per AGP Specification 2.0 |
AgpSBO# |
in/out |
AGP Snoop Back Off Signal. Operates as per AGP Specification 2.0 |
AgpSDone |
in/out |
AGP Snoop Done Signal. Operates as per AGP Specification 2.0 |
AgpPipe# |
s/t/s (in) |
AGP Pipelined Request Signal. Operates as per AGP Specification 2.0 |
AgpSBA[0:7] |
in |
AGP SideBand Address Signals. Operates as per AGP Specification 2.0 |
AgpRBF# |
in |
AGP Read Buffer Full Signal. Operates as per AGP Specification 2.0 |
AgpWBF# |
in |
AGP Write Buffer Full Signal. Operates as per AGP Specification 2.0 |
AgpST[0:2] |
out |
AGP Status Bus. Operates as per AGP Specification 2.0 |
AgpAD_STB0 |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 0. Operates as per AGP Specification
2.0 |
AgpAD_STB0# |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 0. Operates as per AGP Specification
2.0 |
AgpAD_STB1 |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 1. Operates as per AGP Specification
2.0 |
AgpAD_STB1# |
s/t/s (in/out) |
AGP Differential AD Bus Strobe 1. Operates as per AGP Specification
2.0 |
AGPTypeDet |
in |
AGP Type Detect. Operates as per AGP Specification 2.0 |