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7. DLX and the F-CPU

The DLX CPU architecture was designed by H&P as a logical outcome of their research into RISC. Although it was never implemented exactly as described in their book Quantitative Approach, it is so similar to the many commercial RISC implementations that at least a parallel can be drawn between the DLX projected performance and the actual performance of MIPS, SPARC, etc.

The similarity between the Freedom CPU architecture and the DLX hypothetical CPU is not an accident. Basing ourselves on RISC concepts is a natural consequence of the desire to obtain the best performance from a (conceptually) simple design.

In designing the F-CPU architecture, we are also feeling compelled to make use of GCC DLX machine descriptions, DLX simulation and emulation tools, and the vast amount of information freely available on the Web about DLX. If possible, well avoid reinventing the wheel.

However, the F-CPU design is right now so different from DLX that it cannot be called a DLX descendent.


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