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The Freedom CPU ISA and Register Organization

Andrew D. Balsa (maintainer/coordinator)

Rev. 0.0.2, 24 September 1998


Describes the F-CPU ISA (Instruction Set Architecture) and Register Organization, discusses current choices.

1. Acknowledgments

2. Introduction

3. Mission statement

4. Terminology

5. Notation

6. Early architectural choices

7. DLX and the F-CPU

8. Instruction Classes

9. Memory Windows and Virtual Registers

10. Addressing modes

11. Virtual memory: pure paging

12. CPU control registers (CCRs)

13. FP coprocessor TTA architecture

14. Block Move coprocessor architecture


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