FCPU MANUAL REV. 0.2 |
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Please visit us at http://www.f-cpu.org and send comments to the F-CPU mailing list at f-cpu@egroups.com.
This manual is distributed under the terms of the GFDL, or "GNU Free Documentation License", which text can be found on the GNU web site (http://www.gnu.org). A copy of this licence is included in fdl.htm.
Copyright (c) 1999-2000 The F-CPU Group Design Team.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.1
or any later version published by the Free Software Foundation;
with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.
A copy of the license is included in the section entitled "GNU _BR _TAB Free Documentation License".
Everything in this document is furiously preliminary and changes often without notice. Please keep in touch with the group on the mailing list and check the latest updates on the official F-CPU web site.
This document is (C) The F-CPU Group Design Team and is a collaborative work. Anybody can participate to the F-CPU effort and become a team member by subscribing to the mailing lists and taking part to the discussions. You are welcome to submit your ideas and report errors. We are conscious that this document always contains errors but we are working on (or around ?) them constantly.
The manual is split in several parts so any part can be updated independenly, thus easing the parallel work of the group members : a single modification can be made without needing to have the whole document in its latest updated form.
Why a HTML manual ? Because it is the most portable and readable publication format. One can find a Web browser on almost any machine of this planet, and it is also very compact, it has a certain "style" that is usually masked in other publication formats, anybody can modify the source with his text editor and immediatly enjoy the result without the need of a compilation of any kind. I agree that it lacks the possibility to say which page contains what, but this detail is left to the people who will translate this manual in other formats before printing.
created July 8, 1999 by Whygee (Yann Guidon)
July 10 : added some more.
11th : adapted for converstion to PDF with HTMLDOC.
8/2, 8/8, 8/9, 8/13 : added yet some more.
8/25 : reworked a bit (what-why, TTA, endianness, paging, jump station...)
11/5 : merged with some other non-architectural contents.
11/16 : revamped it all for HTML back.
2/27 : major revision of the instruction encoding. Imm6 disappears and most of the old errors/mistypings are corrected.
3/15 : Adapted the CPP macro processing (at last)
You can contact the maintainer of this document by e-mailing Yann Guidon at whygee@f-cpu.org.
The F-CPU main site : http://www.f-cpu.org
The official F-CPU sites : http://f-cpu.tux.org and http://www.f-cpu.de
A little personal page about it : http://www.mime.up8.edu/~whygee/f-cpu.html
The latest update of the F-CPU Manual : http://www.mime.up8.edu/~whygee/fcpu_manual.zip
The mailing lists :
Part 1 : The F-CPU Project, description and philosophy
1.1 Description of the F-CPU project
1.2 Frequently Asked Questions
1.2.1 Philosophy
1.2.2 Tools
1.2.3 Architecture
1.2.4 Performance
1.2.5 Compatibility
1.2.6 Cost/Price/Purchasing
1.3 The genesis of the F-CPU Project
1 History
2 The Freedom GNU/GPL'ed architecture
3 Developing the Freedom architecture : issues and challenges
4 Tools
5 Conclusion
6 Appendix A Ideas for a GPL'ed 64-bit high performance processor design
7 Appendix B Freedom-F1 die area / cost / packaging physical characteristics
8 Appendix C Legal issues / financial issues
1.4 A bit of F-CPU history
1.4.1 M2M
1.4.2 TTA
1.4.3 Traditional RISC
1.5 The design constraints
1.6 The project roadmap
Part 2 : General description of the F-CPU
2.1 The main chacteristics
2.2 The instructions are 32-bit wide
2.3 Register 0 is "read-as-zero/unmodifiable"
2.4 The F-CPU has 64 registers
2.5 The F-CPU is a variable-size processor
2.6 The F-CPU is SIMD-oriented
2.7 The F-CPU has generalized registers
2.8 The F-CPU has special registers
2.9 The F-CPU has no stack pointer
2.10 The F-CPU has no condition code register
2.11 The F-CPU is endianless
2.12 The F-CPU uses paged memory
2.13 The F-CPU stores the state of a task in Context Memory Blocks
2.14 The F-CPU can use the CMBs to single-step tasks
2.15 The F-CPU uses a simple protection mechanism
Part 3 : General description of the FCPU Core #0
3.1 About the FC0 core
3.1.1 The FC0 is superpipelined
3.1.2 The FC0 core implements an out of order completion pipeline
3.1.3 The FC0 uses a scoreboard
3.1.4 The FC0 uses a crossbar
3.2 Evolution of the FC0
3.3 The FC0 Execution Units
3.3.1 The "ROP2" unit
3.3.2 The "bit scrambling" unit
3.3.3 The "increment" unit
3.3.4 The add/sub unit
3.3.5 The integer multiply unit
3.3.6 The integer divide unit
3.3.7 The Load/Store unit
3.3.8 Other units
Part 4 : Advanced topics
4.1 Foreword
4.2 The exceptions
4.3 The Smooth Register backup mechanism
Part 5 : The F-CPU Instruction Set Architecture
5.1 Designing an instruction set
5.2 Instruction formats
5.3 The ISA modularity
5.4 The 2r1w format and its extensions
5.5 Flags
5.5.1 Size flags
5.5.2 SIMD flag
5.5.3 IEEE flag
5.5.4 saturate/carry flag
5.5.5 Endian flag
5.5.6 Stream Hint flag
5.5.6 other flags / reserved fields
Part 6 : F-CPU Instruction Set draft
6.0 Preliminary opcode map overview
6.1 Arithmetic Operations
6.1.1 Core Arithmetic operations
6.1.1.1 add, adds, addc, sadd, sadds, saddc
6.1.1.2 sub, subb, subf, ssub, ssubb, ssubf
6.1.1.3 mul, mulh, muls, mulsh, smul, smulh, smuls, smulsh
6.1.1.4 div, divs, divm, divms, sdiv, sdivs, sdivm, sdivms
6.1.2 Optional Arithmetic operations
6.1.2.1 addi, saddi
6.1.2.2 subi, ssubi
6.1.2.3 muli, smuli
6.1.2.4 divi, sdivi
6.1.2.5 mod, mods, smod, smods
6.1.2.6 modi, smodi
6.1.2.7 mac, macs, mach, machs, smac, smacs, smach, smachs
6.1.2.8 addsub, addsubs, saddsub, saddsubs
6.1.2.9 popcount, spopcount
6.1.3 Optional increment-based operations
6.1.3.1 inc, sinc
6.1.3.2 dec, sdec
6.1.3.3 neg, sneg
6.1.3.4 scan, sscan, lsb1, lsb0, msb1, msb0, slsb1, slsb0, smsb1, smsb0
6.1.3.5 cmpl, scmpl
6.1.3.6 cmple, scmple
6.1.3.7 cmpli, scmpli
6.1.3.8 cmplei, scmplei
6.1.3.9 abs, sabs
6.1.3.10 max, smax
6.1.3.11 min, smin
6.1.3.12 maxi, smaxi
6.1.3.13 mini, smini
6.1.3.14 sort, ssort
6.1.4 Optional Logarithmic Number System operations
6.1.4.1 ladd, sladd
6.1.4.2 lsub, slsub
6.1.4.3 l2int, sl2int
6.1.4.4 int2l, sint2l
6.2 Bit Shuffling based operations
6.2.1 Core Shift and Rotate operations
6.2.1.1 shiftl, sshiftl
6.2.1.2 shiftr, sshiftr
6.2.1.3 shiftra, sshiftra
6.2.1.4 rotl, srotl
6.2.1.5 rotr, srotr
6.2.2 Optional Bit Shift and Rotate operations
6.2.2.1 shiftli, sshiftli
6.2.2.2 shiftri, sshiftri
6.2.2.3 shiftrai, sshiftrai
6.2.2.4 rotli, srotli
6.2.2.5 rotri, srotri
6.2.2.6 bitop, sbitop, bchg, bset, bclr, btst, sbchg, sbset, sbclr, sbtst
6.2.2.7 bitopi, sbitop, bchgi, bseti, bclri, btsti, sbchgi, sbseti, sbclri, sbtsti
6.2.3 Optional Bit Shuffling operations
6.2.3.1 bitrev, bitrevo
6.2.3.2 bitrevi, bitrevio
6.2.3.3 byterev, sbyterev
6.2.3.4 mix (mixl, mixh)
6.2.3.5 expand, (expandl, expandh)
6.2.3.6 sdup
6.3 Logic operations
6.3.1 Core Logic operations
6.3.1.1 logic, or, orn, and, andn, xor, nxor, not, nor, nand
6.3.2 Optional Logic operations
6.3.2.1 logici, andi, andni, ori, xori
6.4 Floating Point Operations
6.4.1 Level 1 Floating Point Operations
6.4.1.1 fadd, sfadd, faddx, sfaddx
6.4.1.2 fsub, sfsub, fsubx, sfsubx
6.4.1.3 fmul, sfmul, fmulx, sfmulx
6.4.1.4 f2int, sf2int, f2intx, sf2intx
6.4.1.5 int2f, sint2f, int2fx, sint2fx
6.4.1.6 fiaprx, fiaprxx, sfiaprx, sfiaprxx
6.4.1.7 fsqrtiaprx, fsqrtiaprxx, sfsqrtiaprx, sfsqrtiaprxx
6.4.2 Level 2 Floating Point Operations
6.4.2.1 fdiv, fdivx, sfdiv, sfdivx
6.4.2.2 fsqrt, fsqrtx, ssqrt, ssqrtx
6.4.2 Level 3 Floating Point Operations
6.4.3.1 flog, flogx, sflog, sflogx
6.4.3.2 fexp, fexpx, sfexp, sfexpx
6.4.3.3 fmac, fmacx, smac, smacx
6.4.3.4 faddsub, faddsubx, sfaddsub, sfaddsubx
6.5 Memory Access operations
6.5.1 Core Memory Access operations
6.5.1.1 load, loade
6.5.1.2 store, storee
6.5.2 Optional Memory Access operations
6.5.2.1 load, loade
6.5.2.2 store, storee
6.5.2.3 loadi, loadie
6.5.2.4 storei, storeie
6.5.2.5 loadf, loadfe
6.5.2.6 loadif, loadife
6.5.2.7 storef, storefe
6.5.2.8 storeif, storeife
6.5.2.9 cachemm
6.6 Data move operations
6.6.1 Core Data move operations
6.6.1.1 move
6.6.1.2 loadcons
6.6.1.3 loadconsx
6.6.1.4 get
6.6.1.5 put
6.6.2 Optional Data move operations
6.6.2.1 loadm
6.6.2.2 storem
6.6.2.3 geti
6.6.2.4 puti
6.7 Instruction Flow Control Operations
6.7.1 Core Instruction Flow Control instructions
6.7.1.1 jmpa
6.7.1.2 loadaddr, loadaddrd
6.7.1.3 loopentry
6.7.1.4 loadaddri, loadaddrid
6.7.1.5 loop
6.7.1.6 syscall, trap
6.7.1.7 halt
6.7.1.8 rfe
6.7.2 Optional Instruction Flow Control instructions
6.7.2.1 srb_save
6.7.2.2 srb_restore
6.7.2.3 serialize
Part 7 : Programming the F-CPU
7.1 Introduction
7.2 Pseudo-superscalar
In the future :
Part 9 : Implementing the F-CPU
Part 8 : The F-CPU Application Binary Interface
Annex documents :
Appendix A : ALPHABETICALLY ORDERED MNEMONIC REFERENCE (not finished)
Appendix B : The F-CPU Opcode map overview (not finished)
SR.h : definition of the numbers and the names of the Special Registers
f-cpu_map.h : definition of the opcode values and names
Figures :
figure 1 : The pipeline is folded around the Xbar.
figure 2 : The first F-CPU chip proposal.
figure 3 : A more precise, first-attempt F-CPU description.
figure 4 : A third F-CPU description
figure 5 : Detail of the ROP2 unit.
figure 6 : Description of the COMBINE function on top of ROP2 for a byte-wide SIMD packet.
figure 7 : Overview of the Scrambling unit
figure 8 : Overview of the Increment Unit
figure 9 : Overview of the Load/Store Unit
figure 10 : Detail of one bit of the SRB flags and decision mechanism.
figure 11 : Preliminary overview of the instruction forms
figure 12 : Description of the mix instruction
figure 13 : Description of the expand instruction