Pin Descriptions
 
 
Pin Description Overview
SysAD Bus Pins
SysAD[0:63] in/out Processor Address/Data Bus. 64
SysADC[0:7] in/out Processor Address/Data Check Bus. 8
SysCMD[0:8] in/out Processor Command Bus. 9
RdRdy out Indicates that the corelogic is ready to acceot a new read transaction. 1
WrRdy out Indicates that the corelogic is ready to accept a new write transaction. 1
ExtRequest out Indicates that the corelogic needs to use the SysAD bus. 1
Release in Indicates that the processor has released the bus to the corelogic. 1
ValidIn in Indicates that data placed on the SysAD/SysCmd busses by the processor is valid. 1
ValidOut out Indicates that data placed on the SysAD/SysCmd busses by the corelogic is valid. 1
IvdAck out Indicates the successful completion of a pending processor invalidate or update request. 1
IvdErr out Indicates the unsuccessful completion of a pending processor invalidate or update request. 1
All pins operate as per MIPS R4x00 SysAD Bus.
Total of 89 pins.
Memory Bus Pins
MemD0[0:63] in/out SDRAM Memory Data Bus 0. 64
MemD1[0:63] in/out SDRAM Memory Data Bus 1. 64
MemA[0:14] out SDRAM Memory Address Bus. 15
MemECC[0:7] in/out SDRAM Memory EC/ECC Bus. 9
MemBS[0:15] out SDRAM Bank Select Signals. 16
MemCS[0:2] out Device Chip Select 0-2 Signals. 3
MemCS[3]/BootCS out Device Chip Select 3/Boot ROM CS Signal. 1
MemDM[0:7] out SDRAM Data Mask Bus. 8
MemDS[0:8] in/out DDR SDRAM Data Strobes. 9
MemRAS[0:3] out SDRAM Row Address Command Indicators. 4
MemCAS[0:3] out SDRAM Column Address Command Indicators. 4
MemWE[0:3] out SDRAM Write Enable Command Indicators. 4
MemCKE[0:7] out SDRAM Clock Enable Indicators. 8
MemReset# out DDR SDRAM Reset. Low (Asserted) at corelogic reset. 1
MemCLK out SDRAM Clock Signal. 1
MemCK0 out DDR SDRAM Differential Clock Signal. 1
MemCK0# out DDR SDRAM Differential Clock Signal. 1
All pins operate as per SDRAM/DDR SDRAM specification.
Total of 212 pins.
Peripheral Interface Bus
FBus[0:63] in/out 64-bit data/address bus. operates either in 1 address + 8 data cycle bursts, and multiples thereof, or in 1 address + 1 data cycle mode. 64
FBusReq# in Request for bus from F-Southbridge 1
FBusGnt# out Grant of bus to F-Southbridge 1
Total of 66 pins.
Miscellaneous Pins
Reset# in F-Corelogic Reset Signal. F-Corelogic exits reset state on the rising edge of Reset# 1
VCC F-Corelogic Power. 1.5V? 3V? 5V? ?
GND F-Corelogic Ground. ?
PicInt[0:15] in PIC Interrupt Signals. Operates as per F-CPU PIC Specification 1.0. 32
PicNMI in PIC Non-Maskable Interrupt Signal. Operateas as per F-CPU PIC Specification 1.0. 1
I2c_SDA in/out I2C Bus Serial Data. Operates as per I2C Specification ?.?. 1
I2c_SCK out I2C Bus Serial Clock. Operates as per I2C Specification ?.?. 1
CPUDet[0:3] in When input voltage is VCC, indicates presense of CPU. 4
Total of 29+? pins. 
Grand total of 396+? pins.