F-CPU Design Team
FCPU MANUAL REV. 0.2

add :        integer ADDition

Forms :
add r3, r2, r1
adds r3, r2, r1
addc r3, r2, r1
sadd r3, r2, r1
sadds r3, r2, r1
saddc r3, r2, r1

Function :
       Computes r1 = r2 + r3

Description :
       add performs an integer addition of the two source operands (r3 + r2) and puts the result in the destination operand (r1).

Format :

size : 8 6 6 6 6
bits : 0                 7 8             13 14             19 20             25 26             31
function : OP_ADD Flags Reg 3 Reg 2 Reg 1

    Flags     Syntax Values Function
8-9 .q, .d or .b postfix * Defines the size parameter
10 s- prefix 1 if set Defines if the operation is SIMD
11 (none yet) 0 Reserved
12 -s postfix 1 if set Saturation flag
13 -c postfix 1 if set Carry flag ( 2r2w )


Remarks :
       - The -s flag implementation is not mandatory.
       - When the -c and -s flags are both set, the instruction saturates with signed ceilings instead of unsigned ceilings (see 5.5.4 saturate/carry flag). This is not mandatory and traps if the implementation does not support this in hardware.
       - On some implementations, when one source operand is zero, the instruction can be transformed into a mov.

 

Examples :

Scalar :

R1 contains 0xF8 (we only consider the lower byte in the registers)
R2 contains 0x0F

add.b r1,r2,r3 : r3 = 0x07 (default behaviour)
adds.b r1,r2,r3 : r3 = 0xFF (saturation)
addc.b r1,r2,r3 : r3 = 0x07, r4= 0x01 (carry)

SIMD :

R1 contains 0x000000F800000001 (in a 64-bit system)
R2 contains 0x0000000F00000002

sadd.b r1,r2,r3 : r3 = 0x0000000700000003 (default behaviour)
sadds.b r1,r2,r3 : r3 = 0x000000FF00000003 (saturation)
saddc.b r1,r2,r3 : r3 = 0x0000000700000003 , r4= 0x0000000100000000 (carry)

Performance (FC0 only) :

Execution Unit :   Add/Sub Unit
Latency :   1 cycle for 8-bit data, 2 cycles for 16-bit to 64-bit data
Throughput :   1 operation per cycle per ASU.
Scheduling :  
Cycle         1                 2                 3                 4                 5                 6                 7        
byte chunks : Stage     Fetch Decode/
Register Read
Xbar ASU(1) Xbar Register
write
  word chunks :   Stage     Fetch Decode/
Register Read
Xbar ASU(1) ASU(2) Xbar Register
write

 


_add.html march 3rd, 2000 by Whygee