Freedom CPU Project
F-CPU Design Team
Draft & Request For Comment 1999.11.16 by Yann GUIDON

 
 
FCPU MANUAL REV. 0.1
 

 

 

Please send comments to the F-CPU mailing list at f-cpu@egroups.com.

 


 

Foreword :

       Everything in this document is furiously preliminary and changes often without notice. Please keep in touch with the group on the mailing list and check the latest updates on the official F-CPU web site.

       This document is (C) The F-CPU Group Design Team and is a collaborative work. Anybody can participate to the F-CPU effort and become a team member by subscribing to the mailing list and taking part to the discussions. You are welcome to submit your ideas and report errors.

 


 

Revision history :

created July 8, 1999 by Whygee (Yann Guidon)
July 10 : added some more.
11th: adapted for converstion to PDF with HTMLDOC.
8/2, 8/8, 8/9, 8/13: added yet some more.
8/25 : reworked a bit (what-why, TTA, endianness, paging, jump station...)
11/5 : merged with some other non-architectural contents.
11/16 : revamped it all for HTML back.
 

You can contact the author of this document by e-mailing Yann Guidon at whygee@mime.up8.edu.

 


 

Hyperlink jump station :

The official F-CPU site : http://f-cpu.tux.org/

The latest update of the F-CPU Manual : http://www.mime.up8.edu/~whygee/fcpu_manual.zip

The mailing list : http://www.eGroups.com/list/f-cpu

 


 

Summary :

Part 1: The F-CPU Project, description and philosophy
       1.1 Description of the F-CPU project
       1.2 Frequently Asked Questions
             1.2.1 Philosophy
             1.2.2 Tools
             1.2.3 Architecture
             1.2.4 Performance
             1.2.5 Compatibility
             1.2.6 Cost/Price/Purchasing
       1.3 The genesis of the F-CPU Project
             1 History
             2 The Freedom GNU/GPL'ed architecture
             3 Developing the Freedom architecture : issues and challenges
             4 Tools
             5 Conclusion
             6 Appendix A Ideas for a GPL'ed 64-bit high performance processor design
             7 Appendix B Freedom-F1 die area / cost / packaging physical characteristics
             8 Appendix C Legal issues / financial issues
       1.4 A bit of F-CPU history
             1.4.1 M2M
             1.4.2 TTA
             1.4.3 Traditional RISC
       1.5 The design constraints

Part 2: General description of the F-CPU
       The main chacteristics
       The instructions are 32-bit wide
       Register 0 is "read-as-zero/unmodifiable"
       The F-CPU has 64 registers
       The F-CPU is a variable-size processor
       The F-CPU is SIMD-oriented
       The F-CPU has generalized registers
       The F-CPU has special registers
       The F-CPU has no stack pointer
       The F-CPU has no condition code register
       The F-CPU is endianless
       The F-CPU uses paged memory
       The F-CPU stores the state of a task in Context Memory Blocks
       The F-CPU uses the CMBs to single-step tasks
       The F-CPU uses a simple protection mechanism

Part 3: General description of the FCPU Core #0
       The FC0 core
       The FC0 is superpipelined
       The FC0 core implements an out of order completion pipeline
       The FC0 uses a scoreboard
       The FC0 uses a crossbar
       The FC0 Execution Units
             The "ROP2" unit
             The "bit scrambling" unit
             The "increment" unit
             The add/sub unit
             The multiply unit
             The divide unit
             The Load/Store unit
             Other units

Part 4: Advanced topics
       The exceptions
       The Smooth Register backup mechanism

Part 5: The F-CPU Instruction Set Architecture
       Designing an instruction set

 

Figures :
       figure 1 : The pipeline is folded around the Xbar.
       figure 2 : The first F-CPU chip proposal.
       figure 3 : A more precise, first-attempt F-CPU description.
       figure 4 : Detail of the ROP2 unit.
       figure 5 : Overview of the Scrambling unit
       figure 6 : Detail of one bit of the SRB flags and decision mechanism.
       figure 7 : A third F-CPU description
       figure 8 : Preliminary overview of the instruction forms

 

 


summary.html nov.16 by Whygee