Register Map Overview
Processor Interface Configuration
Processor Global Configuration 0x100
F-Corelogic Configuration
F-Northbridge Register Map Base Address 0x200
F-Southbridge Configuration Address Virtual Register 0x201
F-Southbridge Configuration Data Virtual Register 0x202
Memory Interface Configuration
Memory Global Configuration 0x300
Memory Bank 0 Configuration 0x310
Memory Bank 1 Configuration 0x311
Memory Bank 2 Configuration 0x312
Memory Bank 3 Configuration 0x313
Memory Bank 4 Configuration 0x314
Memory Bank 5 Configuration 0x315
Memory Bank 6 Configuration 0x316
Memory Bank 7 Configuration 0x317
Boot Bank Configuration 0x318
PIC/Timer Configuration
PIC Global Configuration 0x400
PIC Timer 0 Configuration 0x410
PIC Timer 1 Configuration 0x411
PIC Timer 2 Configuration 0x412
PIC Timer 3 Configuration 0x413
PIC IRQ Status 0x420
I2C Configuration
I2C Global Configuration 0x500
I2C Access Address Virtual Register 0x510
I2C Access Data Virtual Register 0x511
Register Map Detail
Processor Interface Configuration
Processor Global Configuration
0:3 Active CPUs RO
4:7 CPU ID (Returns CPU ID of the CPU reading the register) RO
8:10 Processor Interface Clock/Corelogic Clock Ratio
000 0.5
001 1
010 1.5
011 2
100 2.5
101 3
110 3.5
111 4
RW
11:63 Reserved (Write as 0) RO
F-Corelogic Register Map Base Address
0:26 Reserved (Write as 0) RO
27:63 F-Corelogic Register Map Base Address RW
Memory Interface Configuration
Memory Global Configuration
0:7 Enabled Banks RW
8:9 Memory Interface Clock/Corelogic Clock Ratio
00 2/3
01 1
10 5/4
11 4/3
RW
10 DDR Enable RW
11:13 CAS Delay
000  1 cycle
001 2 cycles
010 3 cycles
011 4 cycles
100 5 cycles
101 6 cycles
110 7 cycles
111 8 cycles
RW
14:63 Reserved (Write as 0) RO
Memory Bank x Configuration (same for each bank)
0:18 Reserved (Write as 0) RO
19:26 Memory Bank Size (16MB Granularity) RW
27:63 Memory Bank x Base Address (256MB Granularity) RW
Boot Bank Configuration
0:14 Reserved (Write as 0) RO
15:18 Waitstates
0000 none
0001 1 cycle
0010 2 cycles
0011 3 cycles
0100 4 cycles
0101 5 cycles
0110 6 cycles
0111 7 cycles
1000 8 cycles
  :
1111 15 cycles
RW
19:26 Memory Bank Size (16MB Granularity) RW
27:63 Boot Bank Base Address (256MB Granularity) RW
PIC/Timer Configuration
PIC Global Configuration
PIC Timer x Configuration (same for each counter)
0 Timer mode
0 Halt on Int
1 Restart on Int
RW
1:23 Reserved (Write as 0) RO
24:63 Cycles until interrupt RW
PIC Interrupt Status
0:15 Interrupt Status (writing 1 acknowledges the corresponding interrupt, reading returns currently active interrupts set as 1) RW
16:63 Reserved (Write as 0) RO
I2C Configuration
I2C Global Configuration
0: Reserved RO
I2C Access Address Virtual Register
0:6 I2C Address WO
7:9 I2C Address (10-bit addressing mode, leave as 0 for 7-bit mode) WO
10:63 Reserved (Write as 0) RO
I2C Access Data Virtual Register
0:7 I2C Data (Multiple writes without new addresses are combined) RW
8 End I2C Transaction
9:63 Reserved (Write as 1) RO