Previous Next Table of Contents

10. Addressing modes

We shall refer to the addressing modes as though they would use standard registers. On the other hand, one must keep in mind the fact that each virtual register shadows a memory location. In this sense, there is no register addressing!

Like H&P, we establish a distinction between data addressing modes (which operate on data in the virtual registers and/or memory) and program flow (instruction) addressing modes (which always take as their destination operand the Program Counter).

10.1 Data addressing modes

Immediate

The 32-bit instruction format allows for 16-bit immediate operands (according to H&P, 16-bit immediate data covers 75-80% of all uses of immediate data). This is basically similar to the DLX I-type instruction format, but some elements are re-arranged:

The opcode occupies the 6 most significant bits.

The destination virtual register occupies the following 5 bits.

The source VR follows, with another 5 bits.

The immediate operand comes last, with 16 bits.

Register

These are really three memory operands instructions. The encoding is again similar to the DLX R-type instructions, but as with the I-type instructions, the destination register field comes next to the opcode field.

Displacement

Uses exactly the same format as the immediate addressing mode, but the 16-bit field is used to hold the displacement. According to H&P, 16-bit displacement capture 99% all displacements.

Register indirect or register deferred

Can be synthesized from the displacement addressing mode by setting the displacement field to zero.

Direct or absolute

Can be synthesized from the displacement addressing mode by using VR0 as the base register. This addressing mode is only useful for the I/O and coprocessor address spaces (for OS kernel use).

10.2 Data addressing affectiveness

Obviously, other more sophisticated addressing modes can be synthesized from the basic register and displacement modes, with a slight performance penalty. According to H&P, the basic addressing modes provided above cover from 75% to 99% of the addressing modes in standard benchmark programs.

10.3 Program flow addressing modes

PC-relative

PC-relative Jumps and Branches are available with a 26-bit offset, plus 2 bits since our instructions are aligned on 32-bit words. This 28-bit range provides ample program space (256MB) and ease of linking.

Register indirect with displacement

The destination address is taken from one of the registers, and a 16-bit (+2) displacement is added, resulting in the new PC value.

Register indirect

This is synthesized from the previous mode by setting the immediate field to zero.


Previous Next Table of Contents